Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

ABSTRACT

During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to microstructures, such asadvanced integrated circuits, and, more particularly, to metallizationsystems comprising sophisticated dielectric and conductive materials.

2. Description of the Related Art

In the fabrication of modern microstructures, such as integratedcircuits, there is a continuous drive to steadily reduce the featuresizes of microstructure elements, thereby enhancing the functionality ofthese structures. For instance, in modern integrated circuits, minimumfeature sizes, such as the channel length of field effect transistors,have reached the deep sub-micron range, thereby increasing performanceof these circuits in terms of speed and/or power consumption and/ordiversity of functions. As the size of individual circuit elements isreduced with every new circuit generation, thereby improving, forexample, the switching speed of the transistor elements, the availablefloor space for interconnect lines electrically connecting theindividual circuit elements is also decreased. Consequently, thedimensions of these interconnect lines are also reduced to compensatefor a reduced amount of available floor space and for an increasednumber of circuit elements provided per unit die area, as typically thenumber of interconnections required increases more rapidly than thenumber of circuit elements. Thus, a plurality of stacked “wiring”layers, also referred to as metallization layers, is usually provided,wherein individual metal lines of one metallization layer are connectedto individual metal lines of an overlying or underlying metallizationlayer by so-called vias. Despite the provision of a plurality ofmetallization layers, reduced dimensions of the interconnect lines arenecessary to comply with the enormous complexity of, for instance,modern CPUs, memory chips, ASICs (application specific ICs) and thelike.

Advanced integrated circuits, including transistor elements having acritical dimension of 0.05 μm and even less, may, therefore, typicallybe operated at significantly increased current densities of up toseveral kA per cm² in the individual interconnect structures, despitethe provision of a relatively large number of metallization layers,owing to the increased number of circuit elements per unit area.Consequently, well-established materials, such as aluminum, are beingreplaced by copper and copper alloys, i.e., materials with significantlylower electrical resistivity and improved resistance to electromigrationeven at considerably higher current densities compared to aluminum. Theintroduction of copper into the fabrication of microstructures andintegrated circuits comes along with a plurality of severe problemsresiding in copper's characteristic to readily diffuse in silicondioxide and a plurality of low-k dielectric materials, which aretypically used in combination with copper in order to reduce theparasitic capacitance within complex metallization layers. In order toprovide the necessary adhesion and to avoid the undesired diffusion ofcopper atoms into sensitive device regions, it is, therefore, usuallynecessary to provide a barrier layer between the copper and thedielectric material in which the copper-based interconnect structuresare embedded. Although silicon nitride is a dielectric material thateffectively prevents the diffusion of copper atoms, selecting siliconnitride as an interlayer dielectric material is less than desirable,since silicon nitride exhibits a moderately high permittivity, therebyincreasing the parasitic capacitance of neighboring copper lines, whichmay result in non-tolerable signal propagation delays. Hence, a thinconductive barrier layer that also imparts the required mechanicalstability to the copper is usually formed so as to separate the bulkcopper from the surrounding dielectric material, thereby reducing copperdiffusion into the dielectric materials and also reducing the diffusionof unwanted species, such as oxygen, fluorine and the like, into thecopper. Furthermore, the conductive barrier layers may also form stronginterfaces with the copper, thereby reducing the probability forinducing significant material migration at the interface, which istypically a critical region in view of increased diffusion paths thatmay facilitate current induced material diffusion. Currently, tantalum,titanium, tungsten and their compounds with nitrogen and silicon and thelike are preferred candidates for a conductive barrier layer, whereinthe barrier layer may comprise two or more sub-layers of differentcomposition so as to meet the requirements in terms of diffusionsuppressing and adhesion properties.

Another characteristic of copper significantly distinguishing it fromaluminum is the fact that copper may not be readily deposited in largeramounts by chemical and physical vapor deposition techniques, therebyrequiring a process strategy that is commonly referred to as thedamascene or inlaid technique. In the damascene process, first adielectric layer is formed which is then patterned to include trenchesand/or vias which are subsequently filled with copper, wherein, aspreviously noted, prior to filling in the copper, a conductive barrierlayer is formed on sidewalls of the trenches and vias. The deposition ofthe bulk copper material into the trenches and vias is usuallyaccomplished by wet chemical deposition processes, such aselectroplating and electroless plating, thereby requiring the reliablefilling of vias with an aspect ratio of 5 and more with a diameter of0.3 μm or even less in combination with trenches having a width rangingfrom 0.1 μm to several μm. Electrochemical deposition processes forcopper are well established in the field of electronic circuit boardfabrication. However, for the dimensions of the metal regions insemiconductor devices, the void-free filling of high aspect ratio viasis an extremely complex and challenging task, wherein thecharacteristics of the finally obtained copper-based interconnectstructure significantly depend on process parameters, materials andgeometry of the structure of interest. Since the geometry ofinterconnect structures is substantially determined by the designrequirements and may, therefore, not be significantly altered for agiven microstructure, it is of great importance to estimate and controlthe impact of materials, such as conductive and nonconductive barrierlayers, the dielectric materials and the like, and their mutualinteraction, on the characteristics of the interconnect structure as awhole so as to insure both high yield and the required productreliability. In particular, it is important to identify, monitor andreduce degradation and failure mechanisms in metallization systems forvarious configurations so as to maintain device reliability for everynew device generation or technology node.

Accordingly, a great deal of effort is being made in investigating thedegradation of copper interconnects, especially in combination withlow-k dielectric materials or ultra low-k (ULK) materials having arelative permittivity of 3.0 or even less, in order to find newmaterials and process strategies for forming copper-based lines and viaswith a low overall permittivity and superior reliability.

One failure mechanism which is believed to significantly contribute to apremature device failure is the electromigration-induced materialtransport, particularly along an inter-face formed between the copperand a dielectric cap layer, which may be provided after filling in thecopper material in the trenches and via openings, the side walls ofwhich are coated by the conductive barrier materials. In addition tomaintaining copper integrity, the dielectric cap layer may usually actas an etch stop layer during the formation of the via openings in theinterlayer dielectric. Frequently used materials are, for example,silicon nitride and nitrogen-containing silicon carbide, which exhibit amoderately high etch selectivity to typically employed interlayerdielectrics, such as a plurality of low-k dielectric materials, and alsosuppress the diffusion of copper onto the interlayer dielectric. Recentresearch results seem to indicate, however, that the interface formedbetween the copper and dielectric cap layer is a major diffusion pathfor material transport during operation of the metal interconnect.

Consequently, a plurality of alternatives have been developed in anattempt to enhance the interface characteristics between the copper andthe cap layer having the capability of reliably confining the copper andmaintaining its integrity. For example, it has been proposed toselectively provide conductive materials on top of the copper-containingregion, which may exhibit superior electromigration performance whilenot unduly reducing the overall resistance of the corresponding metalline. For instance, various alloys, such as a compound ofcobalt/tungsten/phosphorous (CoWP), a compound ofnickel/molybdenum/phosphorous (NiMoP) and the like, have proven to bepromising candidates for conductive cap layers, which may significantlyreduce electromigration effects within a corresponding metal line.

Although these compounds provide superior electromigration performance,the implementation of an appropriate manufacturing process flow intowell-established process strategies for forming complex metallizationsystems is associated with significant efforts with respect to preparingthe exposed surface for the corresponding electrochemical depositionprocess. Moreover, frequently, severe defects may be observed inmetallization systems including copper lines with a conductive cap layerformed on the basis of electrochemical deposition techniques, sinceincreased leakage currents and dielectric breakdown events may occur insuch devices compared to devices having a metallization system based ona dielectric cap layer.

In other strategies, the incorporation of certain species into thecopper surface has been proven to be a viable technique for enhancingthe overall electromigration behavior, for instance, in combination witha corresponding cap or etch stop layer. Thus, in some conventionalprocess regimes, the exposed surface of the copper lines may be exposedto a reactive ambient in order to incorporate silicon, nitrogen and thelike for enhancing the surface characteristics of the metal lines priorto depositing the cap or etch stop material. For example, a siliconand/or nitrogen containing species may be supplied into the reactiveambient of a plasma based cleaning process in order to initiate theinter-diffusion of silicon, nitrogen and the like, thereby forming acorresponding copper compound that may significantly enhance the overallsurface characteristics. For instance, silane may be used in acorresponding plasma treatment in order to form a silicon/coppercompound, which may also be referred to as copper silicide and mayprovide the superior electromigration behavior.

Although the electromigration behavior of the copper surface may beenhanced in combination with a dielectric cap layer by initiating asilicon/nitrogen diffusion into the surface area of the copper material,it turns out, however, that the degree of inter-diffusion may bedifficult to control and also the reactive plasma ambient may result insignificant damage of exposed surface areas of sensitive dielectricmaterials, in particular when ULK materials are used in sophisticatedapplications. For this reason, thermo chemical treatments have beenused, for instance, for cleaning the exposed copper surface andinitiating a silicon diffusion into the copper surface in order toobtain the superior electromigration behavior, while avoiding or atleast reducing undue damage of the sensitive dielectric materials. Onthe other hand, the copper/silicon compound forming in and beyond thecopper surface may have a negative effect on the overall conductivity ofthe metal line, in particular in metallization systems requiring highcurrent densities, due to the reduced cross-sectional area, which mayresult in significant signal propagation delays.

The present disclosure is directed to various methods that may avoid, orat least reduce, the effects of one or more of the problems identifiedabove.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure relates to process techniques in whicha superior performance with respect to electromigration may be obtained,while at the same time the overall electrical performance of themetallization system may be enhanced. For this purpose, the materialcharacteristics of highly sensitive low-k and ULK materials may not beunduly deteriorated, or may even be reestablished, after certain processsteps on the basis of a thermo chemical treatment. It has beenrecognized that, for many sophisticated low-k dielectric materials, theoverall behavior of these materials may critically depend on the carboncontents, which may be significantly reduced upon exposure to reactiveplasma ambients, as may typically be applied during correspondingcleaning processes and frequently also during the incorporation of asilicon species into exposed surface areas. Consequently, in someillustrative aspects disclosed herein, a thermo chemical treatment maybe applied which may result in a significantly reduced degree of carbondepletion upon interaction with sensitive low-k dielectric materials,while a copper-containing metal region may have formed thereon aconductive cap layer which may result in superior electromigrationperformance and may also act as an efficient mask during the thermochemical treatment. Consequently, the advantage of a superiorelectromigration performance without sacrificing overall conductivitymay be accomplished by providing the conductive cap layer, while at thesame time the thermo chemical treatment may result in superiorcharacteristics of the low-k dielectric material, wherein, in someillustrative embodiments disclosed herein, a further thermo chemicaltreatment may be performed on the basis of an appropriate processambient, such as a silicon-containing ambient, which may result in acorresponding improvement of surface characteristics of the dielectricmaterial. For example, a certain degree of etch-related damage of thesensitive low-k dielectric material may be “repaired,” thereby enhancingthe surface conditions for the further processing of the semiconductordevice, for instance in view of depositing a further dielectricmaterial, such as an etch stop material or any other transition materiallayer for forming thereon a further low-k dielectric material.

One illustrative method disclosed herein relates to forming ametallization layer for a semiconductor device. The method comprisesforming a conductive cap layer on a surface of a metal region that islaterally embedded in a first dielectric material of the metallizationlayer. Additionally, the method comprises performing a thermo chemicalcleaning treatment on an exposed surface of the first dielectricmaterial in the presence of the conductive cap layer. Furthermore, themethod comprises forming a second dielectric material on the exposedsurface of the first dielectric material and the conductive cap layer.

A further illustrative method disclosed herein comprises forming aconductive cap material on a copper-containing surface of a metal regionof a metallization layer of a semiconductor device, wherein the metalregion is formed in a low-k dielectric material of the metallizationlayer. The method further comprises performing a first thermo chemicaltreatment on an exposed surface of the low-k dielectric material on thebasis of a copper oxide reducing process gas. The method additionallycomprises performing a second thermo chemical treatment on the exposedsurface on the basis of a silicon-containing process ambient afterperforming the first thermo chemical treatment. Moreover, the methodcomprises forming a dielectric material layer on the conductive caplayer and the exposed surface of the low-k dielectric material.

A still further illustrative method disclosed herein relates to forminga metallization layer of a semiconductor device. The method comprisesforming an opening in a low-k dielectric layer and filling the openingwith a copper-containing material so as to form a metal region.Furthermore, a conductive cap layer is formed on the surface of themetal region and a cleaning process is performed on the basis of acopper-reducing gas ambient in the absence of a plasma. Additionally,the method comprises performing a surface modification process on thebasis of a silicon-containing process ambient in the absence of a plasmain the silicon-containing process ambient.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1 a, 1 b and 1 d schematically illustrate cross-sectional views ofa semiconductor device during various manufacturing stages in formingmetallization layers in which a thermo chemical treatment may beperformed on the basis of a conductive cap layer, according toillustrative embodiments; and

FIG. 1 c schematically illustrates the semiconductor device according toa further illustrative embodiment in which an additional thermo chemicaltreatment may be performed so as to further enhance the characteristicsof a sensitive low-k dielectric material according to furtherillustrative embodiments.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

Generally, the present disclosure provides process techniques in whichsuperior electromigration characteristics may be achieved for metalregions in sophisticated metallization systems on the basis of aconductive cap material, while, additionally, undue deterioration ofsensitive low-k dielectric materials, such as carbon depletion,etch-related damage and the like, may be reduced, so that overallperformance of the metallization system may be enhanced due to superiorelectromigration with a desired high conductivity at more stable anduniform characteristics of the dielectric material, for instance in viewof a higher breakdown voltage and the like. To this end, after formingthe conductive cap layer selectively on an exposed metal region, atleast a cleaning process may be performed as a thermo chemicaltreatment, which may be understood as a treatment performed in a processambient that is established without a plasma, i.e., a high fraction ofionized particles. It should be appreciated in this respect that athermo chemical process ambient may be understood as an ambient in whichthe fraction of ionized particles substantially corresponds to afraction that would be obtained by the thermal movement of molecules andatoms according to specified pressure and temperature conditions. Thus,a higher fraction of ionized particles caused by interaction with anelectromagnetic field may not be considered as a thermo chemical processambient.

In some illustrative embodiments disclosed herein, the thermo chemicalcleaning process may be performed on the basis of oxide-reducing gases,such as an ammonia gas and/or a nitrogen gas, and may result in anefficient removal of contaminants generated during the precedingprocesses, such as copper deposition, chemical mechanical polishing ofexcess materials, the deposition of the conductive cap layer and thelike, while also reducing the tendency of the sensitive low-k dielectricmaterial for out-diffusion of carbon species, which may significantlyaffect the overall characteristics of the low-k material. Consequently,during the further processing, for instance the deposition of a furtherdielectric material, which may be accomplished on the basis of an insitu process in combination with the previous thermo chemical treatment,enhanced surface conditions may be provided which may result inincreased dielectric strength of the dielectric material, which in turnmay contribute to a superior reliability of the resulting metallizationsystem. In other illustrative embodiments, a further thermo treatmentmay be performed on the basis of the silicon-containing process ambientin which a certain degree of surface modification may be accomplished,for instance by hardening or densifying exposed surface areas of thesensitive low-k dielectric material, thereby providing further enhancedsurface conditions during the further processing, or even reducing thedegree of damage of previously performed etch and resist stripprocesses, thereby also contributing to superior reliability and thusdielectric strength. In some illustrative embodiments, the thermochemical treatment may thus be performed as an in situ process sequencewith a cleaning step and a subsequent “silicon diffusion” step, possiblyin combination with a deposition process for forming a furtherdielectric material, such as a silicon nitride material,nitrogen-containing silicon carbide material and the like. Thus, insophisticated metallization systems requiring even further reducedparasitic capacitance values between closely spaced metal regions,sensitive dielectric materials having a dielectric constant of 3.0 oreven 2.0 and less may be used, wherein a corresponding process sequencemay result in a significant degree of damaging the materials, therebycontributing to reduced reliability in terms of dielectric strength andthe like. Thus, an efficient silicon diffusion into the exposed surfaceareas on the basis of a plasma-free treatment may thus reestablish to acertain degree the desired molecular structure or may provide enhancedhardness or density of the surface area, which may also in part enhancemechanical stability to these materials, which may frequently beprovided in the form of a porous material system. For example, thedegree of porosity at the exposed surface areas of these sensitivedielectric materials may be reduced by establishing a process ambientduring the thermo chemical treatment on the basis of silicon-containingsubstances in the form of HMDS (hexamethyldisilazane) and the like. Insome illustrative embodiments, the thermo chemical treatment may also beperformed prior to actually forming the metal regions in the sensitivedielectric material, that is, after patterning the dielectric materialand prior to forming a conductive barrier material and depositing acopper-containing metal. Also, in this case, a negative effect ofplasma-based processes may be avoided while nevertheless obtainingsuperior surface conditions for the subsequent process steps.

FIG. 1 a schematically illustrates a cross-sectional view of asemiconductor device 100 comprising a substrate 101 in and above whichmay be formed circuit elements, such as transistors and the like, asrequired by the overall circuit configuration of the device 100. Aspreviously indicated, the continuous shrinkage of the critical featuresizes in the transistor level of the device, which may currently be atapproximately 50 nm and less, also requires a corresponding adaptationof the feature sizes of metal lines and vias in a metallization system130 of the device 100. In the embodiment shown in FIG. 1 a, themetallization system 130 may be represented by a first metallizationlayer 110 and a second metallization layer 120. It should beappreciated, however, that the metallization system 130 may comprise anynumber of metallization layers as are necessary in view of the overallcomplexity of the device 100. For convenience, any further metallizationlayers which may be formed above the layer 120 or which may bepositioned below the metallization layer 110 are not shown. Themetallization layer 110 may comprise a dielectric material 111, such asa low-k dielectric material having a dielectric constant of 3.0 or less,while, in more sophisticated applications, the dielectric constant maybe approximately 2.0 and less, in which case corresponding materials mayalso be referred to herein as ultra low-k (ULK) materials. Moreover, themetallization layer 110 may comprise a metal region or metal line 112wherein it should be appreciated that, typically, a large number ofappropriate metal regions may be provided in the metallization layer110. The metal line or metal region 112 may comprise a highly conductivecore material 112A based on copper, silver and the like, while aconductive barrier material 112B may confine the core materials 112A,for instance with respect to diffusion into the surrounding dielectricmaterial and with respect to the incorporation of reactive components,such as oxygen, fluorine and the like, which may be present in thedielectric material 111. Furthermore, as previously explained, theconductive barrier material 112B may provide the desired adhesion of thecore material 112A to the surrounding dielectric material 111 and mayalso form a strong interface with the highly conductive core material112A in order to provide the desired electromigration behavior. Forexample, tantalum, tantalum nitride and the like are well-establishedbarrier materials. Furthermore, in the embodiment shown, a conductivecap layer 112C may be formed on the core material 112A and may becomprised of any appropriate material, such as CoWP compounds and thelike, as is for instance also previously explained. It should beappreciated, however, that in other illustrative embodiments (notshown), the conductive cap layer 112C may not be provided if consideredappropriate for the metallization layer 110, while, however, in othermetallization layers, such as the layer 120, superior electromigrationbehavior in combination with a high electric conductivity may berequired. Furthermore, a dielectric etch stop or cap layer 113, whichmay be comprised of silicon carbide, nitrogen-containing siliconcarbide, silicon nitride and the like, may be formed on the dielectricmaterial 111 and on the metal region 112, for instance on the conductivecap layer 112C, while in other cases the dielectric layer 113 mayprovide the required copper confinement and electromigration behavior.

The metallization layer 120 may comprise a dielectric material 121,which may also represent a low-k dielectric material or a ULK material,which may have a more or less porous state, as previously explained.Furthermore, a metal region 122 may be laterally embedded in thedielectric material 121 and may comprise a core material 122A, such as acopper material, in combination with a conductive barrier material 122B.In the embodiment shown, the metal region 122 may comprise a metal line122L and a via 122T connecting to the metal region 112 of themetallization layer 110. Furthermore, in this manufacturing stage, aconductive cap layer 122C formed of any appropriate metal or metalcompound may be formed at least on the core material 122A so as toprovide superior electromigration behavior while not unduly affectingthe overall conductivity of the metal region 122.

The semiconductor device 100 as illustrated in FIG. 1 a may be formed onthe basis of the following processes. After forming correspondingcircuit elements, such as transistors, in a semiconductor materialprovided above the substrate 101, a contact structure (not shown) may beformed on the basis of well-established process techniques in order toprovide an interface between the circuit elements formed in and abovethe semiconductor material and the metallization system 130. Thereafter,one or more metallization layers may be formed, such as the layer 110.For this purpose, the dielectric material 111 may be deposited on thebasis of any appropriate deposition technique, such as chemical vapordeposition (CVD), spin-on techniques and the like, depending on the typeof material to be deposited. As previously explained, the material 111may comprise a certain fraction of carbon species, which maysignificantly affect the overall material characteristics. For example,materials on the basis of silicon, carbon, hydrogen and oxygen mayfrequently be used in a more or less porous state, while in other casespolymer materials and the like may be used. Thereafter, the dielectricmaterial 111 may be patterned on the basis of sophisticated lithographyand etch strategies, as will also be explained with reference to themetallization layer 120. Finally, respective openings corresponding tothe metal region 112 may be filled with a metal-containing material andany excess material thereof may be removed, for instance by chemicalmechanical polishing (CMP) so as to provide electrically isolated metalregions in the dielectric material 111. Thereafter, the conductive caplayer 112C may be formed, if required, followed by the deposition of thedielectric layer 113. Thereafter, the dielectric material 121 may bedeposited as is previously explained with reference to the material 111and a corresponding patterning sequence may be performed so as to obtaina trench and a via opening for the metal line 122L and the via 122T,respectively. After the patterning of the dielectric material 121 on thebasis of well-established etch techniques, in some illustrativeembodiments (not shown), an appropriate thermo chemical treatment may beperformed, as will be explained later on with reference to FIGS. 1 b and1 c. Thereafter, the conductive barrier material 122B may be depositedfollowed by the deposition of the core 122A and the removal of anyexcess material thereof Next, the device 100 may be exposed to adeposition ambient 102, which may represent an electrochemicaldeposition ambient or a gaseous ambient, for instance a CVD ambient, anambient for physical vapor deposition, such as sputter deposition andthe like. For example, a plurality of metal materials may be efficientlydeposited on the basis of electrochemical deposition techniques, forinstance electroless plating, in which an exposed surface of the corematerial 122A may act as a catalyst material for initiating a depositionof the material from an appropriate electrolyte solution. Consequently,a very selective material deposition may be achieved without requiringany additional patterning strategies for restricting the conductive caplayer 122C to the metal line 122L. In other cases, any other appropriatedeposition regime may be used, for instance selective CVD-likedeposition techniques, in which the core material 122A may have asignificantly higher deposition rate compared to exposed surface areas121S of the dielectric material 121.

FIG. 1 b schematically illustrates the semiconductor device 100 whenexposed to a process ambient of a first thermo chemical treatment 103A.The process ambient of the treatment 103A may be established in anyappropriate process tool, such as a deposition chamber and the like, if,for instance, a deposition of a further dielectric material may beperformed as an in situ process. In one illustrative embodiment, theprocess ambient of the treatment 103A may be established on the basis ofa copper-reducing gas, which may, for instance, be established on thebasis of ammonia (NH₃) and nitrogen (N₂) at a pressure of approximately1-6 Torr. For instance, the ratio of ammonia and nitrogen gas may rangefrom approximately 1:400-1:1, while in other cases even substantiallypure ammonia may be used as the reducing gas. Moreover, the substrate101 may be heated to approximately 250-500° C., for instance toapproximately 350° C., in order to establish a desired processtemperature for the treatment 103A. Consequently, a thermally inducedchemical cleaning process may be initiated at the surface of the caplayer 122C and also on the surface 121S of the dielectric material 121.As previously indicated, the treatment 103A may result in the removal ofmetal residues, which may have been generated during the previousprocess sequences, for instance the deposition of the materials 122A,122B and the corresponding removal of any excess material thereof.Furthermore, also during the subsequent process for depositing theconductive cap layer 122C, residues may have deposited in the exposedsurface 121S, which may be efficiently removed, while also reducing thedegree of carbon depletion, which may typically be observed uponplasma-based cleaning processes.

FIG. 1 c schematically illustrates the semiconductor device 100according to a further illustrative embodiment in which the device 100may, in addition to the thermo chemical treatment 103A (FIG. 1 b), beexposed to a further thermo chemical treatment 103B. For instance, thetreatments 103A, 103B may be performed on the basis of an appropriateprocess ambient without exposing the device 100 to ambient atmospherebetween the treatments 103A and 103B. A corresponding sequence ofprocesses may also be referred to as an in situ process sequence,irrespective of whether the processes of the sequence may be performedin the same or different process chambers, as long as an undue exposureto ambient atmosphere may be avoided. The thermo chemical treatment 103Bmay be performed on the basis of a gaseous ambient including, in oneillustrative embodiment, a silicon-containing gas component, such assilane or any derivatives thereof, such as tri methyl silane (3MS),tetra methyl silane (4MS), HMDS and the like. For example, on the basisof an appropriate temperature, such as 250-500° C. for silane or anyderivatives thereof, a corresponding silicon diffusion into the exposedsurface 121S may be initiated, thereby providing a certain degree ofhardening or densification of the surface 121S. In other cases, HMDS maybe used for enhancing the surface conditions of the material 121,thereby even “reestablishing” a desired structure of the surface 121S,which may have been damaged in the preceding process steps. It should beappreciated that a required degree of silicon diffusion into the surface121S may be readily determined on the basis of corresponding testmeasurements in which different dielectric materials may be treated onthe basis of different parameter settings for the treatment 103B anddetermining the surface conditions after the various treatments.Consequently, the exposed surface 121S may be modified so as to provideenhanced surface conditions during the further processing, for instanceduring the deposition of a further dielectric material, thereby reducingthe probability of affecting the characteristics of the material 121,which may thus result in enhanced reliability, as previously explained.At the same time, the cap layer 122C may act as a protection layer so asto avoid undue silicon diffusion into the core material 122A, which mayotherwise result in a reduced overall conductivity, as also previouslydiscussed.

FIG. 1 d schematically illustrates the semiconductor device 100 whenexposed to a deposition ambient 104 after performing the treatment 103A(FIG. 1 b) and, in some illustrative embodiments, also the treatment103B (FIG. 1 c). The deposition ambient 104 may be established on thebasis of appropriate process parameters and precursor materials in orderto obtain a desired composition of a dielectric layer 123, which may actas an etch stop material or any other appropriate transition layer forforming thereon a further dielectric material. In one illustrativeembodiment, the deposition process 104 represents one process of aprocess sequence comprising at least the treatment 103A (FIG. 1 b),wherein the process sequence may be performed as an in situ process inthe above-defined sense. In other illustrative embodiments, additionallythe treatment 103B (FIG. 1 c) may be performed and may also represent apart of the process sequence, wherein the deposition ambient 104 may beestablished in the same process chamber as the process ambient of thetreatment 103B. For this purpose, in some illustrative embodiments, aplasma may be established so as to initiate the deposition of silicon,nitrogen and carbon in order to form the dielectric layer 123. Thus,during the deposition of the material layer 123, the enhanced surface121S obtained by the previous one or more of the thermo chemicaltreatments may result in enhanced deposition uniformity and thus stableand reliable overall characteristics, such as enhanced dielectricstrength and the like. It should be appreciated that any desiredmaterial composition may be deposited during the process 104, such astwo or more different material layers in the form of silicon carbide,silicon nitride, nitrogen-containing silicon carbide and the like.

Thereafter, the further processing may be continued by depositing afurther dielectric material, such as a ULK material and the like, andforming therein appropriate metal lines and vias, as is also describedwith reference to the metallization layers 110 and 120.

In some illustrative embodiments, the thermo chemical treatments 103A,103B, as described with reference to FIGS. 1 b and 1 c, respectively,may be applied as a process sequence after the patterning of thedielectric material 121, as discussed above. For example, during thepatterning of the dielectric material 121, sophisticated etch strategiesmay have to be applied requiring formation of a resist mask, possibly incombination with hard mask material, so as to etch through thedielectric layer 121 and forming a corresponding trench for the metalline 122L (FIG. 1 a). Thus, after this complex patterning sequence, therepeated exposure to a reactive ambient, such as anisotropic etchrecipes, resist strip processes and the like, may result in asignificant degree of damage of exposed surface portions of thedielectric material 121. In this case, applying the sequence oftreatments 103A, 103B of FIGS. 1 b and 1 c may result in an efficientremoval of contaminants and also in a corresponding “reinforcement” ofexposed surface portions of the dielectric material 121. Consequently,carbon depletion during the further processing may be reduced andenhanced surface conditions may also be obtained, for instance, byhardening or densifying the exposed surface areas. Thus, upon depositingthe conductive barrier material 122B, a more reliable degree of coveragemay be obtained since the degree of porosity and etch damage at thesurface areas of the material 121 may be significantly reduced.Furthermore, due to the avoidance of a plasma in the sequence 103A,103B, additional damage may be avoided.

As a result, the present disclosure provides techniques in whichenhanced electro-migration behavior may be accomplished on the basis ofa conductive cap layer while, additionally, enhanced materialcharacteristics of sensitive dielectric materials may be obtained byusing a plasma-free cleaning process, possibly in combination with asurface modification process on the basis of, for instance, asilicon-containing process ambient.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1. A method of forming a metallization layer of a semiconductor device,the method comprising: forming a conductive cap layer on a surface of ametal region, said metal region being laterally embedded in a firstdielectric material of said metallization layer; performing a thermochemical cleaning treatment on an exposed surface of said firstdielectric material in the presence of said conductive cap layer; andforming a second dielectric material on said exposed surface of saidfirst dielectric material and said conductive cap layer.
 2. The methodof claim 1, wherein said thermo chemical cleaning treatment is performedby using oxide-reducing gases.
 3. The method of claim 2, wherein saidoxide-reducing gases comprises at least one of an ammonia gas and anitrogen gas.
 4. The method of claim 1, wherein said thermo chemicaltreatment is performed at a process temperature of approximately250-500° C.
 5. The method of claim 1, wherein said first dielectricmaterial is a carbon-containing material having a dielectric constant ofapproximately 2.7 or less.
 6. The method of claim 1, wherein said thermochemical cleaning treatment and depositing of said second dielectricmaterial are performed as a process sequence without exposing saidsemiconductor device to ambient atmosphere.
 7. The method of claim 1,further comprising performing a second thermo chemical treatment on thebasis of a silicon-containing ambient after performing said thermochemical treatment and prior to forming said second dielectric material.8. The method of claim 6, wherein said silicon-containing ambient isestablished on the basis of at least one of silane, tri-methyl silane,tetra-methyl silane and hexamethyldisilazane (HMDS).
 9. The method ofclaim 1, wherein said metal region comprises copper and a conductivebarrier material.
 10. A method, comprising: forming a conductive capmaterial on a copper-containing surface of a metal region of ametallization layer of a semiconductor device, said metal region beingformed in a low-k dielectric material of said metallization layer;performing a first thermo chemical treatment on an exposed surface ofsaid low-k dielectric material on the basis of a copper oxide reducingprocess gas; performing a second thermo chemical treatment on saidexposed surface on the basis of a silicon-containing process ambientafter performing said first thermo chemical treatment; and forming adielectric material layer on said conductive cap layer and said exposedsurface of said low-k dielectric material.
 11. The method of claim 10,wherein said silicon-containing process ambient is established on thebasis of at least one of silane, tri-methyl silane, tetra-methyl silaneand hexamethyldisilazane (HMDS).
 12. The method of claim 10, whereinsaid reducing process gas comprises at least one of an ammonia gas and anitrogen gas.
 13. The method of claim 10, wherein said first and secondthermo chemical treatments are performed at a process temperature ofapproximately 250-500° C.
 14. The method of claim 10, wherein saidsecond thermo chemical treatment and forming of said dielectric materiallayer are performed as a continuous process sequence without exposingsaid semiconductor device to ambient atmosphere.
 15. The method of claim14, wherein said first thermo chemical treatment, said second thermochemical treatment and forming of said dielectric material layer areperformed as a continuous process sequence without exposing saidsemiconductor device to ambient atmosphere.
 16. The method of claim 10,further comprising forming a trench in said low-k dielectric materialand filling said trench with a copper-containing material so as to formsaid metal region, wherein at least one further thermo chemicaltreatment is performed prior to filling said trench.
 17. The method ofclaim 16, wherein performing at least one further thermo chemicaltreatment comprises performing a second thermo chemical treatment on thebasis of a silicon-containing process ambient.
 18. A method of forming ametallization layer of a semiconductor device, the method comprising:forming an opening in a low-k dielectric layer; filling said openingwith a copper-containing material so as to form a metal region; forminga conductive cap layer on a surface of said metal region; performing acleaning process on the basis of a copper reducing gas ambient in theabsence of a plasma; and performing a surface modification process onthe basis of a silicon-containing process ambient in the absence of aplasma in said silicon-containing process ambient.
 19. The method ofclaim 18, further comprising forming a dielectric material layer on saidlow-k dielectric material and said conductive cap layer.
 20. The methodof claim 18, wherein said low-k dielectric material comprises carbon.